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Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
This supplemental information applies to the GS816118/36T datasheet, which you will find attached to this document. This supplement includes a new package offering (the 165-bump BGA--Package D), as well as an additional organization (x32, which is only offered in the 165 BGA for this part).
1/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA--x18 Commom I/O--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQB NC LBO 2 A A NC DQB DQB DQB DQB MCL NC NC NC NC NC NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A18 A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A19 NC DQA DQA DQA DQA DQA ZZ NC NC NC NC NC A17 A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
2/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA--x32 Common I/O--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC NC DQC DQC DQC DQC FT DQD DQD DQD DQD NC NC LBO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD NC NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A18 A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC NC DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A17 A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
3/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
165 Bump BGA--x36 Common I/O--Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC DQC DQC DQC DQC DQC FT DQD DQD DQD DQD DQD NC LBO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD NC NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A18 A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA A17 A A B C D E F G H J K L M N P R
11 x 15 Bump BGA--13mm x 15 mm Body--1.0 mm Bump Pitch
4/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
GS816118/32/36D 165-Bump BGA Pin Description
Symbol
A0, A1 An A17, A18, A19 DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 BA, BB, BC, BD NC CK BW GW E1 E3 E2 G ADV ADSC, ADSP ZZ FT LBO TMS TDI TDO TCK MCL VDD VSS VDDQ
Type
I I I I/O I -- I I I I I I I I I I I I I I O I -- I I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Byte Write--Writes all enabled bytes; active low Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active l0w Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply
5/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Package Dimensions--165-Bump FPBGA (Package D)
A1 CORNER TOP VIEW BOTTOM VIEW O0.10 M C O0.25 M C A B O0.40~0.50 (165x) A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H I J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 1.0
150.07
14.0
A
0.450.05 0.25 C
1.0
1.0
0.15 C
B 0.20(4x)
130.07
6/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0.25~0.40 1.20 MAX.
(0.26)
C
SEATING PLANE
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Ordering Information
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32
Part Number1
GS816118D-250 GS816118D-225 GS816118D-200 GS816118D-166 GS816118D-150 GS816118D-133 GS816132D-250 GS816132D-225 GS816132D-200 GS816132D-166 GS816132D-150 GS816132D-133 GS816136D-250 GS816136D-225 GS816136D-200 GS816136D-166 GS816136D-150 GS816136D-133 GS816118D-250I GS816118D-225I GS816118D-200I GS816118D-166I GS816118D-150I GS816118D-133I GS816132D-250I GS816132D-225I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6
TA3
C C C C C C C C C C C C C C C C C C I I I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816136AD-100IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
7/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Revision: 9/26/02
GS816118/32/36D
Supplemental Datasheet Information
Ordering Information
Org
512K x 32 512K x 32 512K x 32 512K x 32 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS816132D-200I GS816132D-166I GS816132D-150I GS816132D-133I GS816136D-250I GS816136D-225I GS816136D-200I GS816136D-166I GS816136D-150I GS816136D-133I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA 165 BGA
Speed2 (MHz/ns)
200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5
TA3
I I I I I I I I I I
Status
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816136AD-100IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
8/8 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features
* IEEE 1149.1 JTAG-compatible Boundary Scan * 2.5 V or 3.3 V +10%/-10% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA
1M x 18, 512K x 36 18Mb Sync Burst SRAMs
Flow Through/Pipeline Reads
250 MHz-133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data Output Register.
SCD Pipelined Reads
The GS816118/36T is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Functional Description
Applications
The GS816118/36T is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Core and Interface Voltages
The GS816118/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Rev: 2.12 9/2002 1/32 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
GS816118 100-Pin TQFP Pinout
VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC
NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M X 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 A18 NC NC BB BA A17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC
Rev: 2.12 9/2002
LBO A5 A4 A3 A2
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A1 A0 TMS TDI VSS VDD TDO TCK A10 A11 A12 A13 A14 A15 A16 2/32 (c) 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
GS816136 100-Pin TQFP Pinout
DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6 A7 E1 A18 BD BC BB BA A17 VDD VSS CK GW BW G ADSC ADSP ADV A8 A9
DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9
LBO A5 A4 A3 A2 A1 A0 TMS TDI VSS VDD Rev: 2.12 9/2002 3/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDO TCK A10 A11 A12 A13 A14 A15 A16 (c) 1999, Giga Semiconductor, Inc.
GS816118/36T-250/225/200/166/150/133
TQFP Pin Description Symbol
A0, A1 A2-A18 A19 DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 NC BW BA, BB, BC, BD CK GW E1 G ADV ADSP, ADSC ZZ TMS TDI TDO TCK FT LBO VDD VSS VDDQ
Type
I I I I/O -- I I I I I I I I I I I O I I I I I I
Description
Address field LSBs and Address Counter preset Inputs Address Inputs Address Input Data Input and Output pins No Connect Byte Write--Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply
Rev: 2.12 9/2002
4/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
GS816118/36 Block Diagram
Register
A0-An
D
Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1
A
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q 36 D 36
Register
D BB
Q 4 4
Register
D BC
Q
Register
D
Q
Register
D BD
Q
Register 4
Register
D
Q
36 36 36
E1
Register
D
Q
36 32 Parity Encode 4 Parity Compare 36
Register
D
Q
FT G Power Down Control
ZZ
1
DQx1-DQx9
NC
D NC
Note: Only x36 version shown for simplicity.
Rev: 2.12 9/2002
5/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q
Q D
Register
GS816118/36T-250/225/200/166/150/133
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control
Pin Name
LBO FT ZZ
State
L H L H or NC L or NC H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
Note: There arepull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 01 10 11 00 10 11 00 01 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.12 9/2002
6/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Byte Write Truth Table Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Note: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version.
Rev: 2.12 9/2002
7/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Synchronous Truth Table Operation
Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X R R W CR CR CW CW
E1
H L L L X H X H X H X H
ADSP
X L H H H X H X H X H X
ADSC
L X L L H H H H H H H H
ADV
X X X X L L L L H H H H
W3
X X F T F F T T F F T T
DQ4
High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.12 9/2002
8/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low.
Rev: 2.12 9/2002
9/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 2.12 9/2002
10/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to 4.6 -0.5 to 6 -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
oC o
C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 2.12 9/2002
11/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Power Supply Voltage Ranges Parameter
3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
3.0 2.3 3.0 2.3
Typ.
3.3 2.5 3.3 2.5
Max.
3.6 2.7 3.6 2.7
Unit
V V V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
2.0 -0.3 2.0 -0.3
Typ.
-- -- -- --
Max.
VDD + 0.3 0.8 VDDQ + 0.3 0.8
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
-- -- -- --
Max.
VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 2.12 9/2002
12/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKC VDD + 2.0 V
VSS 50% VSS - 2.0 V 20% tKC
50% VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Layer Board
single four --
Symbol
RJA RJA RJC
Max
40 24 9
Unit
C/W C/W C/W
Notes
1,2 1,2 3
Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.12 9/2002
13/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2
Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
Output Load 1 DQ 50 VDDQ/2 * Distributed Test Jig Capacitance 30pF*
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IIN1 IIN2 IOL VOH2 VOH3 VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -8 mA, VDDQ = 2.375 V IOH = -8 mA, VDDQ = 3.135 V IOL = 8 mA
Min
-1 uA -1 uA -1 uA -100 uA -1 uA -1 uA 1.7 V 2.4 V --
Max
1 uA 1 uA 100 uA 1 uA 1 uA 1 uA -- -- 0.4 V
Rev: 2.12 9/2002
14/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 0 to 70C -40 to 85C Unit 300 40 190 20 270 20 175 10 300 30 190 20 270 15 175 10 30 30 90 65 20 80 60 20 30 30 85 65 155 10 165 10 150 10 20 20 75 50 235 15 245 15 215 15 225 15 160 10 30 30 80 55 170 20 180 20 165 15 175 15 155 15 185 10 140 10 20 20 64 50 265 30 275 30 240 25 250 25 205 20 215 20 165 15 195 10 150 10 30 30 70 55 155 10 165 10 150 10 160 10 140 10 150 10 135 10 190 20 150 15 170 10 135 10 20 20 60 50 235 20 245 20 215 15 225 15 185 15 195 15 170 15 180 15 145 10 200 20 160 15 180 10 145 10 30 30 65 55 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 155 10 125 10 170 15 140 10 155 10 125 10 20 20 50 45 265 35 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 150 10 165 10 135 10 180 15 150 10 165 10 135 10 30 30 55 50
mA mA mA mA mA mA mA mA mA mA mA mA
-225 0 to 70C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C 0 to 70C
-200
-166
-150
-133
Rev: 2.12 9/2002 Pipeline (x36) Flow Through Pipeline (x18) Flow Through IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB 20 20 85 60 ISB IDD IDD 165 10 260 15 180 20 290 30 Pipeline (x36) Flow Through Pipeline (x18) Flow Through Pipeline -- Flow Through Pipeline -- Flow Through IDD 165 10 IDD IDDQ 260 20 IDD IDDQ 180 20 IDD IDDQ 290 40
Parameter
Test Conditions
Operating Current
3.3 V
Device Selected; All other inputs VIH or VIL Output open
15/32
Operating Current
2.5 V
Device Selected; All other inputs VIH or VIL Output open
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Standby Current
ZZ VDD - 0.2 V
Deselect Current
Device Deselected; All other inputs VIH or VIL
GS816118/36T-250/225/200/166/150/133
(c) 1999, Giga Semiconductor, Inc.
Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
GS816118/36T-250/225/200/166/150/133 AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR -250 Min 4.0 -- 1.5 1.5 1.2 0.2 5.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 2.5 -- -- -- -- -- 5.5 -- -- -- -- -- -- 2.3 2.3 -- 2.3 -- -- -- -225 Min 4.4 -- 1.5 1.5 1.3 0.3 6.0 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 2.7 -- -- -- -- -- 6.0 -- -- -- -- -- -- 2.5 2.5 -- 2.5 -- -- -- -200 Min 5.0 -- 1.5 1.5 1.4 0.4 6.5 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 3.0 -- -- -- -- -- 6.5 -- -- -- -- -- -- 3.0 3.2 -- 3.0 -- -- -- -166 Min 6.0 -- 1.5 1.5 1.5 0.5 7.0 -- 3.0 3.0 1.5 0.5 1.3 1.5 1.5 -- 0 -- 5 1 20 Max -- 3.4 -- -- -- -- -- 7.0 -- -- -- -- -- -- 3.0 3.5 -- 3.0 -- -- -- -150 Min 6.7 -- 1.5 1.5 1.5 0.5 7.5 -- 3.0 3.0 1.5 0.5 1.5 1.7 1.5 -- 0 -- 5 1 20 Max -- 3.8 -- -- -- -- -- 7.5 -- -- -- -- -- -- 3.0 3.8 -- 3.0 -- -- -- -133 Min 7.5 -- 1.5 1.5 1.5 0.5 8.5 -- 3.0 3.0 1.5 0.5 1.7 2 1.5 -- 0 -- 5 1 20 Max -- 4.0 -- -- -- -- -- 8.5 -- -- -- -- -- -- 3.0 4.0 -- 3.0 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 2.12 9/2002
16/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Write Cycle Timing
Single Write Burst Write
Write
Deselected
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV
tS tH ADV must be inactive for ADSP Write
WR2 WR3
A0-An GW
WR1
tS tH
tS
tH
BW
tS tH
BA-BD
tS tH
WR1 WR1
WR2
WR3 WR3
E1 masks ADSP
E1
E1 only sampled with ADSP or ADSC
G
tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B D2C D2D D3A
DQA-DQD
Hi-Z
D1A
Rev: 2.12 9/2002
17/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Flow Through Read Cycle Timing
Single Read
CK
tS tH tKH tS tH
tKL tKC
Burst Read
ADSP is blocked by E inactive
ADSP ADSC
tS tH
ADSC initiated read
Suspend Burst
Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW BA-BD
tS tH
E1 masks ADSP
E1
tOE tOHZ
G
tOLZ tKQX Q1A tLZ tHZ tKQ Q2A Q2B Q2c Q2D Q3A tKQX
DQA-DQD
Hi-Z
Rev: 2.12 9/2002
18/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Flow Through Read-Write Cycle Timing
Single Read Single Write
Burst Read
CK
tS tH tKH tKL tKC tS tH ADSP is blocked by E inactive ADSC initiated read
ADSP ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS
tH
GW
tS tH
BW
tS tH
BA-BD
tS tH
WR1
E1 masks ADSP
E1
tOE tOHZ
G DQA-DQD
Hi-Z tKQ Q1A tS tH Q2A Q2B Q2c Q2D Q2A
D1A
Burst wrap around to it's initial state
Rev: 2.12 9/2002
19/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Pipelined SCD Read Cycle Timing
Single Read Burst Read tKH tKL tKC tS tH ADSP is blocked by E inactive
CK
tS tH
ADSP ADSC
tS tH
ADSC initiated read
Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW
BWA-BWD
tS tH
E1 masks ADSP
E1
tOE
G DQA-DQD
Hi-Z tOLZ Q1A tLZ tKQ
tOHZ tKQX Q2A Q2B Q2c Q2D
tKQX Q3A tHZ
Rev: 2.12 9/2002
20/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Pipelined SCD Read-Write Cycle Timing
Single Read tKL
Single Write
Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS tH
GW
tS tH
BW
tS tH
BWA-BWD
tS tH
WR1
E1 masks ADSP
E1
tOE
tOHZ
G DQA-DQD
Hi-Z tKQ Q1A
tS tH D1A Q2A Q2B Q2c Q2D
Rev: 2.12 9/2002
21/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tS tH
tKC
tKH tKL
ADSP ADSC
tZZS
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Rev: 2.12 9/2002 22/32 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
~~ ~~
tZZH
~ ~
tZZR
~~ ~~
CK
~ ~~~~ ~ ~ ~~~~ ~
GS816118/36T-250/225/200/166/150/133
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 2.12 9/2002
23/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
JTAG TAP Block Diagram
0
Bypass Register
210
Instruction Register TDI ID Code Register
31 30 29
TDO
*
* **
210
Boundary Scan Register
n
******
***
210
TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Presence Register 0 1 1
Die Revision Code Bit # x36 x18
Not Used
I/O Configuration
GSI Technology JEDEC Vendor ID Code
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 011011001 0 011011001
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 2.12 9/2002 24/32 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions
BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The Rev: 2.12 9/2002 25/32 (c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU BYPASS
Code
000 001 010 011 100 101 110 111
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 2.12 9/2002
26/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
2.0 -0.3 0.6 * VDD2 -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV --
Max.
VDD3 +0.3 0.8 VDD2 +0.3 0.3 * VDD2 1 100 1 -- 0.4 -- 100 mV
Unit Notes
V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V DQ
JTAG Port AC Test Load
50 VT = 1.25 V
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted.
Rev: 2.12 9/2002
27/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
JTAG Port Timing Diagram
tTKH TCK tTS tTH tTKL tTKC
TMS
TDI TDO tTKQ
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com.
Rev: 2.12 9/2002
28/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
TQFP Package Drawing L Symbol
A1 A2 b c D D1 E E1 e L L1 Y
c Pin 1
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom. Max
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 22.0 20.0 16.0 14.0 0.65 0.45 0.60 1.00 0.10 0.75 0.10 1.40 0.30 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1
L1
e b
D D1
A1
Y
A2
0
7
E1 E
Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion.
Rev: 2.12 9/2002
29/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36
Part Number1
GS816118T-250 GS816118T-225 GS816118T-200 GS816118T-166 GS816118T-150 GS816118T-133 GS816136T-250 GS816136T-225 GS81613T-200 GS816136T-166 GS816136T-150 GS816136T-133 GS816118T-250I GS816118T-225I GS816118T-200I GS816118T-166I GS816118T-150I GS816118T-133I GS816136T-250I GS816136T-225I GS816136T-200I GS816136T-166I GS816136T-150I GS816136T-133I
Type
Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5
TA3
C C C C C C C C C C C C I I I I I I I I I I I I
Status
Not Available Not Available Not Available
Not Available Not Available Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816118T-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.12 9/2002
30/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; New GS816118T-150IT 1.00 9/ 1999A;GS816118T-150IT 2.00 1/1999B GS816118T 2.01 1/ 2000C;GS816118 T 2.02 1/ 2000D Types of Changes Format or Content Content Page;Revisions;Reason * Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B * Added x72 Pinout. * Added GSI Logo. * Changed pin description in TQFP to match order of pins in pinout. * Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Core and Interface voltages - Changed paragraph to include information for 3.3V;Completeness * Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. * Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness * Electrical Characteristics - Added second Output High Voltage line to table; completeness. * Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. Content * Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 15 from 20 ns to 100 ns * Added 225 MHz speed bin * Updated Pg. 1 table, AC Characteristics table, and Operating Currents table to match 815xxx * Updated format to comply with Technical Publications standards * Updated Capitance table--removed Input row and changed Output row to I/O * Updated Features list on page 1 * Completely reworked table on page 1 * Updated Mode Pin Functions table on page 7 * Added 3.3 V references to entire document * Updated Operating Conditions table * Updated Boundary Scan Chain table * Updated JTAG section * Added Pin 56 to Pin Description table * Updated Operating Currents table and added note * Update table on page 1; added power numbers * Updated Application Tips paragraph
GS18/362.0 1/2000DGS18/ 362.03 2/2000E
GS18/362.03 2/200E; 816118_r2_04 816118_r2_04; 816118_r2_05
Content/Format
816118_2_05; 816118_r2_06 816118_r2_06; 811618_r2_07
Content Content
816118_r2_07; 811618_r2_08
Content
Rev: 2.12 9/2002
31/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816118/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason * Updated Synchronous Truth Table * Updated Operating Currents table * Updated table on page 1; updated power numbers * Updated Recommended Operating Conditions table (added VDDQ references) * Updated table on page 1 * Created recommended operating conditions tables on pages 11 and 12 * Updated AC Electrical Characteristics table * Added Sleep mode description on page 22 * Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) * Updated BSR table (2 and 3 changed to X (value undefined)) * Added 250 MHz speed bin * Deleted 180 MHz speed bin * Updated AC Characteristics table * Updated FT power numbers * Updated Mb references from 16Mb to 18Mb * Removed ByteSafe references * Changed DP and QE pins to NC * Updated ZZ recovery time diagram * Updated AC Test Conditions table and removed Output Load 2 diagram * Removed Preliminary banner * Removed pin locations from pin description table * Removed BSR table
816118_r2_08; 811618_r2_09
Content
816118_r2_09; 816118_r2_10
Content
816118_r2_10; 816118_r2_11
Content
816118_r2_11; 816118_r2_12
Content
Rev: 2.12 9/2002
32/32
(c) 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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